module TLV5618_Driver(
	// 系统相关
	clk		,
	rst_n		,
	// 用户相关
	DAC_data	,
	set_go	,
	set_done	,
	// DAC相关
	DAC_cs_n	,
	DAC_sclk	,
	DAC_din		
);

	input						clk		;
	input						rst_n		;
	input			[15:0]	DAC_data	;
	input						set_go	;
	output reg				set_done	;
	output reg				DAC_cs_n	;
	output reg				DAC_sclk	;
	output reg				DAC_din	;
	
	parameter CLOCK_FREQ = 50_000_000;	// 系统50Mhz
	parameter SCLK_FREQ = 12_500_000;	// 最大20Mhz，这里为了方便分频得到，所以用 12.5Mhz
	parameter MCNT_DIV_CNT = CLOCK_FREQ / (SCLK_FREQ * 2) - 1;
	
	reg [7:0] div_cnt;	// 分频计数器
	reg [5:0] lsm_cnt;	// 序列计数器
	
	reg [15:0] r_DAC_data;
			
	
	reg set_en;		// 设置使能
	
	always@(posedge clk or negedge rst_n)
		if (!rst_n)
			set_en <= 1'd0;
		else if (set_go)
			set_en <= 1'd1;
		else if ((lsm_cnt == 6'd33)&&(div_cnt == MCNT_DIV_CNT))
			set_en <= 1'd0;
		else 
			set_en <= set_en;
	
	// 最小时间计数器
	always@(posedge clk or negedge rst_n)
		if (!rst_n)
			div_cnt <= 8'd0;
		else if (set_en) begin
			if (div_cnt == MCNT_DIV_CNT)
				div_cnt <= 8'd0;
			else 
				div_cnt <= div_cnt + 1'd1;
		end
		else 
			div_cnt <= 8'd0;

	// 序列计数器		
	always@(posedge clk or negedge rst_n)
		if (!rst_n)
			lsm_cnt <= 6'd0;	
		else if (div_cnt == MCNT_DIV_CNT) begin
			if (lsm_cnt == 6'd33)
				lsm_cnt <= 6'd0;
			else 
				lsm_cnt <= lsm_cnt + 1'd1;
		end
		else 
			lsm_cnt <= lsm_cnt;
			
			
	// 线性序列机驱动
	
	always @(posedge clk)
		if (set_go)
			r_DAC_data <= DAC_data;
		else 
			r_DAC_data <= r_DAC_data;
	
	always@(posedge clk or negedge rst_n)
		if (!rst_n) begin
			DAC_cs_n	<= 1'd1;	
		   DAC_sclk	<= 1'd1;	
		   DAC_din	<= 1'd1;	
		end
		else if (div_cnt == MCNT_DIV_CNT) begin
			case (lsm_cnt)
				0 : begin DAC_cs_n <= 1'd0; DAC_din <= r_DAC_data[15];DAC_sclk <= 1'd1;end
				1 : begin DAC_sclk <= 1'd0; end
				2 : begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[14];end
				3 : begin DAC_sclk <= 1'd0; end
				4 : begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[13];end	
				5 : begin DAC_sclk <= 1'd0; end
				6 : begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[12];end	
				7 : begin DAC_sclk <= 1'd0; end
				8 : begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[11];end	
				9 : begin DAC_sclk <= 1'd0; end
				10: begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[10]; end
				11: begin DAC_sclk <= 1'd0; end
				12: begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[9]; end
				13: begin DAC_sclk <= 1'd0; end	
				14: begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[8]; end
				15: begin DAC_sclk <= 1'd0; end
				16: begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[7]; end
				17: begin DAC_sclk <= 1'd0; end	
				18: begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[6]; end
				19: begin DAC_sclk <= 1'd0; end
				20: begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[5]; end
				21: begin DAC_sclk <= 1'd0; end	
				22: begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[4]; end
				23: begin DAC_sclk <= 1'd0; end
				24: begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[3]; end
				25: begin DAC_sclk <= 1'd0; end	
				26: begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[2]; end
				27: begin DAC_sclk <= 1'd0; end
				28: begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[1]; end
				29: begin DAC_sclk <= 1'd0; end	
				30: begin DAC_sclk <= 1'd1; DAC_din <= r_DAC_data[0]; end
				31: begin DAC_sclk <= 1'd0; end
				32: begin DAC_sclk <= 1'd1; end
				33: begin DAC_cs_n <= 1'd1; end
				default: DAC_cs_n <= 1'd1; 
			endcase
		end
		
	// 输出完成信号		
	always@(posedge clk or negedge rst_n)
		if (!rst_n) 
			set_done <= 1'd0;
		else if ((lsm_cnt == 6'd33)&&(div_cnt == MCNT_DIV_CNT))
			set_done <= 1'd1;
		else 
			set_done <= 1'd0;
			
endmodule
